1. Field of Invention
The invention relates to a dynamic random access memory (DRAM) and, in particular, to a refresh-free ultra-low power pseudo DRAM. Such low power products include computer, cell phones, personal digital assistants (PDA""s), digital set-up box, satellite positioning systems, consumption IC""s (TV""s and Game Boys).
2. Related Art
The volatile memories are classified by two types: static random access memory (SRAM) and dynamic random access memory (DRAM). The one-bit cell of SRAM comprises four or six transistors, while one-bit cell of DRAM is comprised of one transistor and one capacitor.
The capacitor of the DRAM needs to be refreshed and charged repeatedly in order to ensure the data storage. The SRAM, on the other hand, is faster in it processing speed and more stable than the usual DRAM. The word xe2x80x9cstaticxe2x80x9d means that the data can be stored for a long period without charging the memory cell. Because of this special property, the SRAM is often used as a buffer memory. Generally speaking, the SRAM is used as a buffer memory, whereas the DRAM plays the role of main memory.
However, as the semiconductor manufacturing technology enters into the nanometer scale, the existing DRAM memory cell consisting of one transistor and one capacitor faces with challenges from the physical limitation of semiconductor devices and the manufacturing limitation for semiconductor capacitors. For example, the capacitor of the available memory cell of DRAM has a more serious problem in leakage current than the transistor. The size of the memory cell will be also affected by the physical properties of semiconductor devices.
Therefore, it is thus highly desirable to provide a new technique for the nanometer semiconductor manufacturing technology to overcome the leakage current problem of the capacitor of the memory cell and the physical limitations of semiconductor devices.
In view of the foregoing problems, it is an objective of the invention to provide a refresh-free DRAM, which uses the memory cells of the SRAM to store data without charging, in replace of DRAM that require to be changed constantly to maintain the data.
Another objective of the invention is to provide an ultra-low power DRAM, which utilizes the low power characteristics of the memory cells of SRAM to reduce the power consumption.
A further objective of the invention is to provide a pseudo DRAM, which uses memory cells of SRAM to substitute for the memory cells of DRAM. An interface control circuit converts a clock for controlling the DRAM into a clock for controlling the SRAM. so that the clock of the SRAM is compatible with DRAM in timing control.
To achieve the above objective, the disclosed refresh-free ultra-low power pseudo DRAM performs a 1-bit read, a 1-bit write, and a non-read and non-write operation according to a clock for controlling the DRAM. It includes one interface control circuit and a SRAM memory cells. An interface control circuit generates a second read-out signal, a second write signal or a second non-read and non-write signal according to the first read-out signal, the first write signal, or the first non-read and non-write signal, respectively. A static random access memory (SRAM) cell is coupled with the interface control circuit for performing the 1-bit read-out according to the second read-out signal, the 1-bit write according to the second write signal, or the non-read and non-write operation according to the non-read and non-write signal.